Data backup memory

To provide a data backup memory that can function, when used to design an LSI, for a circuit operating at a frequency double that of a clock provided. The data backup memory includes a first precharge node, a second precharge node, a first precharge circuit, a second precharge circuit, a first discharge circuit, and a second discharge circuit. It can maintain and improve the characteristics of conventional data backup memories that the setup time therefor is ideally zero and that the worst value of a delay time can be designed to be small, while enabling data processing both at a rising and a falling edges of a clock signal.