A/D converter

An analog input voltage signal to be A/D-converted is supplied to a ring gate delay circuit including inverting circuits connected in series in a ring as a supply voltage thereto. The interval for which a pulse circulates the ring varies with the analog input voltage signal. The number of times circulation of the pulse and the position of the pulse for a predetermined interval are detected by a counter to provide upper bits and by a pulse position detector to provide lower bits of A/D conversion result of the analog input voltage signal, respectively. The counter and the pulse position detector are included in a coding process block which is driven by a constant voltage which is different from the analog input voltage signal to the ring gate delay circuit.