Reduced static phase error CMOS PLL charge pump
An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The outpu...
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| creator | STIFF JONATHON C |
| description | An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The output circuit may be configured to receive the pump up and pump down signals and generate an output signal. The pump up circuit may be configured to precharge the first source bias and the pump down circuit may be configured to precharge the second source bias signal. |
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The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The output circuit may be configured to receive the pump up and pump down signals and generate an output signal. The pump up circuit may be configured to precharge the first source bias and the pump down circuit may be configured to precharge the second source bias signal.</description><edition>7</edition><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021015&DB=EPODOC&CC=US&NR=6466078B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021015&DB=EPODOC&CC=US&NR=6466078B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>STIFF JONATHON C</creatorcontrib><title>Reduced static phase error CMOS PLL charge pump</title><description>An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The output circuit may be configured to receive the pump up and pump down signals and generate an output signal. The pump up circuit may be configured to precharge the first source bias and the pump down circuit may be configured to precharge the second source bias signal.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAPSk0pTU5NUSguSSzJTFYoyEgsTlVILSrKL1Jw9vUPVgjw8VFIzkgsSk9VKCjNLeBhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwWYmZmYG5hZOhsZEKAEAZwYplQ</recordid><startdate>20021015</startdate><enddate>20021015</enddate><creator>STIFF JONATHON C</creator><scope>EVB</scope></search><sort><creationdate>20021015</creationdate><title>Reduced static phase error CMOS PLL charge pump</title><author>STIFF JONATHON C</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US6466078B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>STIFF JONATHON C</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>STIFF JONATHON C</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Reduced static phase error CMOS PLL charge pump</title><date>2002-10-15</date><risdate>2002</risdate><abstract>An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The output circuit may be configured to receive the pump up and pump down signals and generate an output signal. The pump up circuit may be configured to precharge the first source bias and the pump down circuit may be configured to precharge the second source bias signal.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY |
| title | Reduced static phase error CMOS PLL charge pump |
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