Reduced static phase error CMOS PLL charge pump

Reduced static phase error CMOS PLL charge pump

An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The outpu...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: STIFF JONATHON C
Format: Patent
Sprache:eng
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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Beschreibung
Zusammenfassung:An apparatus comprising a pump up circuit, a pump down circuit and an output circuit. The pump up circuit may be configured to generate a pump up signal and receive a first source bias. The pump down circuit may be configured to generate a pump down signal and receive a second source bias. The output circuit may be configured to receive the pump up and pump down signals and generate an output signal. The pump up circuit may be configured to precharge the first source bias and the pump down circuit may be configured to precharge the second source bias signal.