Massively parallel instruction predecoding

A microprocessor configured to predecode variable length instructions in a massively parallel fashion is disclosed. The microprocessor may comprise a prefetch fetch unit configured to read instruction bytes from memory and a plurality of predecode unit configured to receive and predecode the instruction bytes. The predecode units are configured to operate separately and in parallel to generate one or more predecode bits per instruction byte. The microprocessor may further include a predecode bit correction unit configured to receive, verify, and correct the predecode bits from the parallel predecode units. A computer system and method for predecoding instructions are also disclosed.