Circuit and method for partial product bit shifting

A circuit for shifting the number of partial product bits per column in an adder tree is provided. A partial product bit is generated having a weight 22k that has a 1 value only if one input bit of weight 2(k-1) has a 0 value while another input bit of weight 2k has a 1 value. Another more significant partial product bit of weight 2(2k+1) receives the same input bits and has a 1 value only if both of the input bits have a 1 value. In this manner, the number of partial product bits in the column of weight 22k is decreased by 1 while the number of bits is the column of weight 2(2k+1) is increased by 1. Therefore, if the column of weight 22k had the greatest number of partial product bits of all columns, and if the column of weight 2(2k+1) had at least two fewer bits than the column of weight 22k, the total maximum number of bits for all the columns is reduced by 1.