Methods for making semiconductor chip having both self aligned silicide regions and non-self aligned silicide regions

A semiconductor process is provided that creates fully-salicided transistors. in a first region and partially-salicided transistors in a second region. Each of the fully-salicided transistors includes a salicided gate electrode and salicided active regions. Each of the partially-salicided transistors includes a salicided gate electrode and active regions that are free from salicide. A silicide blocking layer prevents the formation of salicide in the active regions of the partially-salicided transistors. The silicide blocking layer is deposited over the first and second regions, and then removed over the first region. The remaining portion of the silicide blocking layer over the second region is then etched back until the upper surfaces of the gate electrodes in the second region are exposed. The remaining portions of the silicide blocking layer covers the active regions in the second region. A refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the active regions and gate electrodes in the first region, but only on the gate electrodes in the second region.