Circuit arrangement and method with state-based transaction scheduling

A data processing system, circuit arrangement, and method rely on state information to prioritize certain transactions relative to other transactions when scheduling transactions in a data processing system. In one implementation, as a result of the recognition that in many shared memory systems cached data having a modified state is accessed more frequently than cached data having a non-modified state, transactions associated with modified cached data are prioritized relative to transactions associated with non-modified cached data, thereby reducing the latency of such modified transactions. Any concurrent increase in latency for non-modified transactions is more than offset by the decreased latency of modified transactions, resulting in an overall reduction in system latency.