Floating gate memory apparatus and method for selected programming thereof

A program element for a memory cell formed in a substrate. The element includes a well region of an opposite conductivity type as said substrate formed in the substrate; a first active region formed in the well and having the same conductivity type as said well; and a second active region formed in the well and having a conductivity type opposite to that of the well, and having a junction with said first active region. In a further aspect, the element is used in a memory cell. The memory cell may be implemented in an array of cells to perform a method of creating a reverse breakdown condition in an array of memory cells arranged in columns and rows in the array. The method includes the steps of: applying a first voltage on a first column node connecting a first column of said cells to bias a first set of wells associated with a first set of cells, and a second voltage on a second column node connecting a second column of said cells to bias a second set of wells associated with a second set of cells; and applying a third voltage on a first row node connecting a first row of said cells intersecting said first and second sets of cells, and applying said second voltage on a second row node connecting a second row of said cells intersecting said first and second sets; wherein the difference between the first voltage and the third voltage creates said reverse breakdown condition in at least one cell occupying said first column and first row.