Compact non-volatile memory device and memory array

A compact non-volatile memory device and memory array that are compatible with conventional MOS device processing. The compact non-volatile memory device includes a PMOS storage transistor with a floating gate in series with a PMOS access transistor. Since both of these PMOS transistors can be disposed in a single N-type well region, the size of the compact non-volatile memory device is relatively small. Another MOS processing compatible compact non-volatile memory device is formed in a semiconductor substrate of a first conductivity type (typically P-type) that includes a well region of a second conductivity type (typically N-type). Such a device also includes first source and drain regions of the first conductivity type, a first channel region defined therebetween, and a floating gate. This device also includes second source and drain regions of the first conductivity type, a second channel region defined therebetween, and a gate. The first and second source and drain regions and first and second channel regions are formed in the well region. The compact non-volatile memory array includes a plurality of traversing bit and word lines and a plurality of the compact non-volatile memory devices. Each compact non-volatile memory device includes a PMOS storage transistor with a floating gate and a serially connected PMOS access transistor. In addition, each compact non-volatile memory device is electrically connected to a bit line via the PMOS storage transistor's source and electrically connected to a word lines via the PMOS access transistor's gate.