Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory

A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests. Similarly, the main memory scheduler prioritizes a majority of read requests ahead of write requests, so that a processor that originates a read request is not normally stalled by a previously issued write request, as would be the case in first-in-first-out (FIFO) issuance of memory requests. The main memory scheduler performs FIFO processing, for example, when a later-received read request and an earlier-received write request both access the same location in main memory, or when the number of pending write requests exceeds a predetermined limit. Such prioritization of requests can be made programmable, depending on signals held in storage elements that are included in the main memory scheduler.