Digital-edge-rate control LVDS driver

A differential output driver circuit produces a differential output signal in response to an input data signal. The differential output driver circuit provides for a controlled edge rate in the differential output signal when the input data signal changes logic states. Control signals are generated using an adjustable delay circuit, each subsequent control signal being delayed in time from the preceding control signal by a unit delay time. The control signals control N output drivers, each of the N output drivers having an output signal coupled to the differential output signal, and each contributing a portion of the differential output signal. When the input data signal changes from one logic state to another, the differential output signal will have a defined edge rate determined by the unit delay time and the contributing portion from each of the N output drivers. In one example, the unit delay time is determined by a delay time through a buffer that has a controlled current limit. The current limit is provided by a current source that is compensated for semiconductor processing variations and temperature variations. Semiconductor processing variations are corrected by producing a current inversely proportional to a MOS transistor's trans-conductance. Since the current limit in the buffer is raised for slower transistors (lower trans-conductance), the unit delay time is compensated when the process parameters vary. The differential output driver circuit provides for minimum over-shoot, low jitter, low distortion, low signal skew, and a controlled rise and fall times over varied common mode voltages.