Process for making a non-volatile memory cell with a polysilicon spacer defined select gate

In accordance with an embodiment of the present invention, a method of forming a memory cell includes: forming a floating gate over a first portion of a silicon body region, the floating gate being insulated from the underlying first portion of the body region; forming a second layer polysilicon over the floating gate and a second portion of the body region, the second layer polysilicon being insulated from the underlying floating gate and the second portion of the body region; and forming a masking layer over the second layer polysilicon, the masking layer having a width along a first dimension parallel to the surface of the body region such that the masking layer extends over an entire width of the floating gate along the first dimension but does not extend beyond edges of steps of the second layer polysilicon formed due to the presence of the floating gate. Among many other advantages, such method provides a means of accurately controlling the cell channel length.