Redundancy method capable of disabling and replacing redundant memory cells that are defective

A redundancy circuit is capable of repeatedly replacing a defective cell with redundant cells. The redundancy circuit is in a semiconductor memory device that includes memory cells and redundant cells in a memory array. The redundancy circuit includes first and second fuse blocks. The first fuse block has a first main fuse and generates a first redundancy signal according to whether the first main fuse is cut. The first redundancy signal indicates whether there is a defective memory cell for the redundancy circuit to replace. The second fuse block has a second main fuse and generates a second redundancy signal according to whether the second main fuse is cut. The second redundancy signal can stop the replacement of the defective cell with the redundant cell when the redundant cell is defective. When the replacement of the defective cell with the redundant cell is stopped, the defective cell is replaced by another redundant cell.