Trench-isolated EEPROM flash in segmented bit line page architecture

An EEPROM floating gate memory device includes: a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 Å to 1000 Å of gate oxide; an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 15 Å to 150 Å of tunnel dielectric; and a control gate disposed over and insulated from the floating gate and the channel between the floating gate and the buried source. Both the floating gate and the channel underneath are self-aligned to and flanked by the field oxide in the trench along the direction perpendicular to the channel current flow. The add-on floating gate forms both a self-aligned endcap on the field oxide and the self-aligned tunnel area on the buried drain. The architecture allows a reduction in memory cell size. The memory cells are particularly suited for a proposed segmented bit line page memory array architecture with the common drain line and the common source line in separate Y-column direction, and with the common control gate line in the X-row direction. A semiconductor device has a gate disposed over the channel and insulated from the channel by the gate oxide, an add-on poly spacer shorted electrically to the gate, and disposed over and insulated from the lightly doped source and drain by oxide. The add-on poly spacer also foams the self-aligned encap of the device on the field oxide.