Semiconductor device array having dense memory cell array and heirarchical bit line scheme

A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an "open" configuration, allowing adjacent unit circuits (202) be accessed simultaneously. The lower conductive segments (204a-204h) are coupled to higher conductive segments (208a-208f) by reconnector circuits (210a and 210b). The higher conductive segments (208a-208f) are arranged into folded pairs (208a/208d, 208b/208e and 208c/208f) between differential-type amplifiers (212a and 212b). The reconnector circuits (210a and 210b) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (210a and 210b) couple adjacent folded higher conductive segment pairs to one another. In a switch configuration, the reconnector circuits (210a and 210b) couple a matching lower conductive segment (204a-204h) to each higher conductive segment of the adjacent higher conductive segment pairs.