Wafer thickness compensation for interchip planarity

An integrated circuit package having a carrier and semiconductor circuit chips are disclosed. The carrier has a topography of mesas projected from its surface. Each of the semiconductor circuit chips has a device side surface and an opposite bottom surface, which has a topography of a recess conversely matching a respective one of the mesas of the carrier for self-alignment positioning on the carrier. To offset the variation in the thickness of the semiconductor circuit chips, the width of the recess in each semiconductor circuit chip is controlled so that the alignment of the recess on its respective mesa elevates the bottom surface of the semiconductor circuit chip. Therefore, the device side surfaces of the semi conductor circuit chips are placed in the same plane.