Use of dummy poly spacers and divot fill techniques for DT-aligned processing after STI formation for advanced deep trench capacitor DRAM

A method of forming a dynamic random access memory cell in a semiconductor substrate. The cell has a transistor in an active area of the semiconductor substrate electrically coupled to a storage capacitor through a buried strap or coupling region. The method includes forming an electrode for the capacitor in a lower portion of a trench in the semiconductor substrate. A sacrificial material is formed on the sidewall portion of the trench, such sacrificial material extending from the surface of the semiconductor substrate into the substrate beneath the surface of the semiconductor substrate. The active area for the transistor is delineated and includes forming a covering material over the surface of the semiconductor substrate with a portion of the sacrificial material being projecting through the covering material to expose such portion of the sacrificial material. Subsequent to the delineation of the active area, the covering material and the exposed portion of the sacrificial material are subjected to an etch to selectively remove the sacrificial material while leaving the covering material, such removed sacrificial material exposing the first region of a semiconductor substrate disposed beneath a surface of such substrate.