Method of etching self-aligned vias to metal using a silicon nitride spacer

A method for manufacturing integrated circuits uses a silicon nitride spacer for etching self-aligned vias. The method is accomplished by (1) providing a first inter-level dielectric layer having metal lines formed on it; (2) depositing a silicon nitride layer over the metal lines and the first inter-level dielectric layer; (3) depositing a second inter-level dielectric layer on the silicon nitride layer; (4) depositing a photoresist on that second inter-level dielectric layer; (5) patterning vias on that second inter-level dielectric layer; (6) non-selectively oxide etching the second inter-level dielectric layer and the silicon nitride layer to form the vias; and (7) selectively nitride-to-oxide etching the silicon nitride layer to remove the silicon nitride layer surrounding the metal lines, where the etching stops at the first inter-level dielectric layer. This forms an access window.