Selective latch for a domino logic gate

An integrated circuit chip includes a domino logic gate, circuitry for selectively latching a logic output signal of the gate and an enable source for the gate. The enable source and gate positions on the chip and a clock driving the chip has a frequency such that the enable signal arrives late at the logic gate during the evaluate phase of each clock cycle. The circuitry for selectively latching is constructed so that the domino logic gate is evaluated or latched during the same clock cycle that the enable signal is derived despite the aforementioned positions and frequency.