Process for fabricating an EEPROM

A method of protecting a tunnel dielectric area from subsequent processing steps in EEPROM fabrication after formation of a memory cell poly 1 floating gate on a P-type substrate, including first implanting the substrate to form a buried N+ junction below and beside the floating gate, and then growing a first thin oxide layer over the N+ junction and on sidewalls of the floating gate and a selection device gate. A thin layer of polysilicon is deposited and then a second thin oxide layer is grown over the thin polysilicon layer. A photoresist is applied, and then removed from the top surface and the sidewalls of the gate structures. The second thin oxide layer is removed from the top surface and the vertical sidewalls of the gate structures. The photoresist is removed, and the thin polysilicon layer and the first thin oxide layer is removed from the sidewalls of the poly 1 floating gate structure, and the polysilicon layer and the second thin oxide layer are removed from the horizontal surfaces except for the area immediately above the tunnel dielectric area and at the base of the sidewalls. With the tunnel dielectric area thus protected, an add-on polysilicon layer is deposited and etched back to form an add-on floating gate at the sidewalls of the floating gate of the memory cell, and the add-on gate to the selection device.