Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance

Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance

Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/mum or below) and a channel length (sub-lithographic, e.g., 0.1 mum or less) that is shorter than the lithog...

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Bibliographische Detailangaben
Hauptverfasser: HANAFI HUSSEIN IBRAHIM, BOYD DIANE CATHERINE, NATZLE WESLEY CHARLES, IEONG MEIKEI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/mum or below) and a channel length (sub-lithographic, e.g., 0.1 mum or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.