Multi-value logic device, bus system of multi-value logic devices connected with shared bus, and network system of information processors loaded with multi-value logic devices and connected with shared network

A multi-value logic device in which a unique bus level is allocated beforehand to each binary logic signal outputted by a function of the multi-value logic device. Upon receipt of the binary logic signal via a bus level selection circuit, a driver converts the binary logic signal to an analog signal with a voltage having an amplitude of e.2n-1, in which n is the bus level of the binary logic signal and e is a reference voltage. When a plurality of binary logic signals are simultaneously inputted, the driver superimposes analog signals in accordance with the bus level of each binary logic signal to generate a multi-value logic signal, so that multiplex communication is realized. A receiver performs an operation reverse to the operation of the driver, and encodes a multi-value logic signal received via a bus to convert the signal to a binary logic signal and transmit the signal to each function. In this manner, the multi-value logic device suppresses an increase in the number of bus signal conductors, and enhances throughput by realizing multiplex communication.