Block redundancy in ultra low power memory circuits

Block redundancy in ultra low power memory circuits

A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) a global signal. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: GRADINARIU JULIAN C, GEORGESCU BOGDAN I, MULHOLLAND SEAN B, ROSE DANNY L, SILVER JOHN J, FORD KEITH A
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) a global signal. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of the enable signals generally reduces current consumption in the memory array.