Dynamic, data-precharged, variable-entry-length, content addressable memory circuit architecture with multiple transistor threshold voltage extensions

A dynamic, data-precharged, variable-entry-length content addressable memory circuit architecture. A match at a particular data bit is found employing precharge/conditional discharge domino logic. Two bits stored at each entry location, data bit and valid bit. The valid bit determines whether the co...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	HILL ANTHONY M
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!