Dynamic, data-precharged, variable-entry-length, content addressable memory circuit architecture with multiple transistor threshold voltage extensions

A dynamic, data-precharged, variable-entry-length content addressable memory circuit architecture. A match at a particular data bit is found employing precharge/conditional discharge domino logic. Two bits stored at each entry location, data bit and valid bit. The valid bit determines whether the corresponding data bit takes part in the match determination. This allows for full flexibility in the matching function including variable-entry-length access. The precharge is data driven. This eliminates clock signal routing to the memory array, reducing crosstalk between clock and data lines and reducing routing congestion. The circuit employs a mix of low threshold voltage and high threshold voltage transistors. The selection of which transistors have low threshold voltage and which have high threshold voltage enables additional speed via low threshold voltage transistors while maintaining low quiescent current via high threshold voltage transistors.