Level shifter circuit

A level shifter circuit of the preferred embodiment can be used as a transfer gate driver of a memory circuit such as a DRAM. A pair of cross-coupled transistors receives a first potential. A plurality of transistors are coupled between the pair of cross-coupled transistors and a second potential. An output unit has a pull-down switch for providing an output signal of one of first, second and third potentials and are coupled to the pair of cross-coupled transistor and the plurality of transistors. The third potential has a potential between the first and second potentials.