Apparatus and method for high density CMOS gate arrays

A base cell, having four sites, for use in a gate array retains the same design rules as a prior art base cell, but the area of the base cell has been reduced. The reduction in the size of the base cell is the result of arranging all transistor pairs to be fabricated over a common moat regions, thereby eliminating areas previously used for moat-to-moat spacing. In addition, at least one moat region is configured to permit a conducting path passing nearby to observe the design rules without appreciable. Components forming the base cell have been rearranged to permit the D-type flip-flop circuit to be implemented using three of the base cell sites instead of the four base cell sites required by the prior art. This component rearrangement is useful for other circuits implemented by the base cell as well.