Source synchronous interface between master and slave using a deskew latch

A source synchronous interface between a master device and slave device is described. A master device having a plurality of deskew latches is coupled to a slave device via a bus. The master device communicates commands and first timing information to the slave device via the bus. In response, the slave device communicates data and second timing information to the master device via the bus. When data is communicated from the slave device to the master device, the data is stored in one of the plurality of deskew latches until accessed by the master device. The plurality of deskew latches ensure that the master device will always read valid data for the full range of skew of the first and second timing information.