Processor-cache protocol using simple commands to implement a range of cache configurations

Processor-cache protocol using simple commands to implement a range of cache configurations

A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A seco...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: HUNT STEVE, SINGH GURBIR, PATTERSON DAN, LEE PHIL G, PRASAD BINDI, MACWILLIAMS PETER
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands that are executed by the second level cache.