Burst access of registers at non-consecutive addresses using a mapping control word

A controller chip has programmable registers that control the operation of the controller chip. The controller chip connects to a microprocessor and bus controller through a bus that performs burst cycles. Although only one address (the starting address) is sent over the bus during the burst cycle, multiple data words are sent in the burst. These data words are written to addresses that follow the starting address in a fixed burst sequence. Programmable registers are accessed in an order that is not the fixed burst sequence. The programmable registers are accessed in a non-sequential order in a single burst cycle by using a mapping control word. The starting address is is set to the address of a mapping control register in the controller chip. The mapping control word is sent as the first data word after the starting address. The mapping control word is decoded to determine which of the programmable registers are to be written during the burst cycle. The following data words in the burst are written to the programmable registers identified by the mapping control word, ignoring the addresses implied by the normal burst sequence. A single burst cycle using the mapping control word can write different programmable registers that normally could not be written together in the same burst cycle.