Method and apparatus for instruction queue compression

A microprocessor having an instruction queue capable of out-of-order instruction dispatch and compaction of unaligned strings of empty storage locations is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations, each coupled to a single destination storage location. The instruction queue may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. As the instructions are output, gaps of empty storage locations may be formed in the queue. The microprocessor may be configured to compact out strings of empty storage locations greater than a predetermined number. This compaction may be performed by selectively shifting the instructions remaining in the queue either zero or N storage locations, wherein N is a predetermined positive integer. This configuration may simplify control logic associated with the queue while still compacting out many of the empty storage locations. A data queue and method for managing a queue are also contemplated, as is a computer system utilizing the above-mentioned microprocessor.