Cell placement method and apparatus for integrated circuit and storage medium having cell placement program for integrated circuit stored thereon

The invention provides a cell placement method and apparatus wherein an area for cell's placement is assured to place cells as many as possible to be placed efficiently on a single chip and a storage medium on which a cell placement program which allows such placement is stored. In the cell placement method and apparatus, in order to design an integrated circuit having a plurality of routing layers, when to place cells in a situation wherein a wire is already routed prior to the placement of the cells is present, placement of each of the cells at a position at which the cell overlaps with the already routed wire is permitted unless a wiring pattern in the cell and the already routed wire overlap with each other in a same routing layer. The invention is applied, in designing an integrated circuit (LSI, VLSI, ASIC or the like) having a plurality of routing layers, for example, a gate array to placement of cells on a chip in a state wherein an already routed wire such as a bulk power supply wire or a clock signal wire routed prior to the placement of the cells is present.