Cycle control circuit for extending a cycle period of a dynamic memory device subarray

A cycle control circuit for use with a memory device subarray and method of operation thereof. The cycle control circuit includes a previous address buffer for storing a last accessed address of the subarray and an address comparator for comparing a current requested address with the last accessed address in the previous address buffer. The cycle control circuit also includes a cycle counter, coupled to the address comparator, that receives a control signal generated by the address comparator and, in response thereto, modifies a reset operation of the subarray. In another aspect, the method includes applying an address to the subarray and generating control signals for the subarray to produce a data output in response to the address. After producing the data output, the applied address is stored. Next, a new address is received and the new address is compared to the stored address. In response to the stored and new addresses being the same, the reset operation of the subarray is modified to again generate the data output in a shorter period of time.