Semiconductor structure for testing vias interconnecting layers of the structure
A wafer for testing a manufacturing process for vias has a large number of vias (millions) formed into strings that have an open circuit resistance if the string contains a defective via and have a resistance of a few thousand ohms if the string is good. A multiplexor circuit is formed on the test w...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A wafer for testing a manufacturing process for vias has a large number of vias (millions) formed into strings that have an open circuit resistance if the string contains a defective via and have a resistance of a few thousand ohms if the string is good. A multiplexor circuit is formed on the test wafer and scans the via strings and produces a binary output denoting that the addressed string is good or defective. The addresses are generated off the wafer by a compute and a defective string is readily identified. |
---|