Method of manufacturing a semiconductor device having conductive patterns

A method of manufacturing a semiconductor device having a fuse conductive pattern is disclosed. The method includes forming a fuse conductive pattern on a silicon substrate and forming a first insulation layer on the fuse conductive pattern and the silicon substrate. The first insulation layer has a first etching speed. The method further includes forming a stopper pattern on a first region of the first insulation layer to cover the fuse conductive pattern and forming a second insulating layer on the stopper pattern and the first insulation layer. The stopper pattern has a second etching speed and the second insulation layer has a third etching speed. A second region of the second insulating layer is etched to form an opening. The second region is within the first region. An etching condition is set such that the first etching speed is higher than the second etching speed so that the stopper pattern is exposed at a bottom of the opening. The exposed stopper pattern is etched with an etching condition that the second etching speed is faster than the third etching speed so that the exposed stopper pattern is removed and the first insulation layer remains on the fuse conductive pattern.