Dynamic clocking apparatus and system for reducing power dissipation

A dynamic clocking computer system for a processor. The dynamic clocking computer system comprises a clock divider circuit, a multiplexer, and a state machine circuit. The clock divider circuit receives a first clock and outputs the first clock and generates a second clock. The second clock is supplied to external circuitry. The state machine circuit is coupled to the clock divider circuit and receives the first and second clocks from the clock divider circuit. The state machine circuit also receives an external access signal indicating an internal clock to select from the first and second clocks. In response to the external access signal, the state machine circuit generates a select signal to enable the multiplexer to select an internal clock. When the selected internal clock is the second clock, the internal clock is synchronized to the second clock. The multiplexer is coupled to the clock divider circuit and receives the first and second clocks through the clock divider circuit. In response to the select signal generated by the state machine circuit, the multiplexer selects an internal clock from the first and second clocks. The internal clock is then provided to the processor. By thus providing a lower clock frequency to the processor for external access operations, the present invention reduces power dissipation.