Parallel power system which includes over voltage protection

A parallel power system with over voltage protection is disclosed. The parallel power system comprises at least two voltage regulators in parallel and an over voltage protection circuit for each of the at least two voltage regulators. The over voltage protection circuit comprises a transistor coupled to an associated voltage regulator and a detector coupled to each of the transistor for shutting off power to the associated voltage regulator if the associated voltage regulator is in an over voltage condition. Through the use of a circuit in accordance with the present invention, the computer processors are protected against being damaged as a result of an over-voltage condition in one of the voltage regulators. Moreover, the over voltage protection circuit in accordance with the present invention will isolate the voltage regulator that is experiencing an over voltage condition and shut it down, without shutting down the entire system.