Architecture and methods for a hardware description language source level debugging system

Architecture and methods for a hardware description language source level debugging system

This invention provides a method for displaying circuit analysis results corresponding to parts of the circuit near the portion of the hardware description language (HDL) specification that generated that part of the circuit. The invention also includes a method for using probe statements in the HDL...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: LIN, JING C, ESTRADA, PAUL, SEAWRIGHT, ANDREW, CHATTERJEE, TRINANJAN, GIRCZYC, EMIL, RAGHVENDRA, SRINIVAS, GREGORY, BRENT
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:This invention provides a method for displaying circuit analysis results corresponding to parts of the circuit near the portion of the hardware description language (HDL) specification that generated that part of the circuit. The invention also includes a method for using probe statements in the HDL specification to mark additional points in the initial circuit that should not be eliminated during optimization. This improves the ability to display circuit analysis results near the appropriate part of the HDL specification.