Computer system with trigger controlled interface and method

An interface (101) in a computer system has an port (150) which is coupled to a memory via a first bidirectional data path (104) and coupled to a peripheral device via a communication path (106). The interface (101) has a controller (170) with a trigger buffer (175) and a pointer register (160). The pointer register (160) provides a movable pointer (165) to memory entries of data queues. The trigger buffer (175) continuously receives and accumulates trigger signals (+E,crc 1+EE +E,crc 2+EE +E,crc 3+EE ) and sends start signals +Z +Z +Z to the pointer register (165). A queue is transmitted through the first path (104), the port (150) and the second path (106) or vice versa when a first trigger (e.g., (+E,crc 1+EE ) signal arrives. The trigger buffer (175) receives further trigger signals (e.g., (+E,crc 2+EE ) and accumulates them in a trigger buffer (175) before it sends start signals (e.g., +Z ) for further transmissions. Optionally, interface 101 provides start signals after prioritizing trigger signals.