Method for forming an asymmetric floating gate overlap for improved device performance in buried bit-line devices

A method of making an electrically erasable non-volatile EPROM memory device and the device itself having an asymmetric floating gate with respect to a buried source region and a buried drain region is disclosed. A patterned floating gate member is formed over a portion of the source region and a portion of the drain region producing a floating gate-to-source overlap and a floating gate-to-drain overlap, respectively, such that the floating gate-to-source overlap is less than the floating gate-to-drain overlap.