Parallel test for asynchronous memory

An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the fist output signals and to produce second output signals indicative of logic states of the first output signals therefor The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry. In a further embodiment, a plurality of cells of an asynchronous memory device may be read in parallel and an output signal indicative of a logical combination of logic states of the plurality of cells and a test signal at the speed of the slowest cell access time produced thereby.