Matrix addressable array for digital xerography

An apparatus for forming an image comprising a substrate with a plurality of high voltage transistors on the substrate. The transistors include a source electrode, a drain electrode and a gate electrode. Each transistor switches a marking potential of several hundred volts between the source and drain by a gate potential of at least an order of magnitude lower than the source to drain potential. There are a plurality of high voltage capacitors on the substrate. One of each capacitor is connected to one of the drain electrodes and each capacitor stores a charge potential approximately equal to the marking potential. The charge potential on each capacitor controls the forming of the image. A first data input on the substrate selectively loads a gate potential on gate the electrodes. A second data input located on the periphery of the substrate selectively loads a source potential on the source electrodes. The high voltage capacitors, the high voltage transistors, and the first data input are thin film elements integrally formed on the substrate.