Opcode compare logic in E-unit for breaking infinite loops, detecting invalid opcodes and other exception checking

A computer processor which has an apparatus in its Execution Unit (E-unit) that detects a match between an opcode about to be executed and opcodes programmed into it by the computer manufacturer provides a method for alleviating design deficiencies in the processor. The E-unit further contains a mechanism for transmitting the opcode and a desired action back to the Instruction Unit (I-unit) where it may be compared with the next instruction that is decoded. Furthermore, the E-unit opcode compare logic contains a mechanism for breaking infinite loops that may result. This E-unit opcode compare mechanism, may also be used for other purposes such as detecting invalid opcodes and other exception checking since it may allow for a faster cycle time of the processor than if this logic were implemented in the I-unit.