Interconnect design with controlled inductance

An integrated circuit device interconnect with controlled inductance. An integrated circuit device includes an insulating layer formed on a substrate and a an interconnect disposed on the insulating layer extending along a first path. A dedicated current return path having one end configured to be coupled to ground is disposed on the first insulating layer parallel to the interconnect, such that the signal received by the interconnect is returned to ground via the dedicated current return path when the dedicated current return path is coupled to ground. Inductance of the interconnect is thus controlled by reducing the area of the circuit loop formed by the interconnect and the parallel dedicated current return path. In one embodiment, the dedicated current return path is formed in an embedded ground plane just above or below the first interconnect. In this embodiment, the interconnect and the dedicated current return path together act as a built-in decoupling capacitor, further offsetting the inductive time constant to approach critical damping.