High performance cost optimized memory with delayed memory writes

High performance cost optimized memory with delayed memory writes

A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core wr...

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Bibliographische Detailangaben
Hauptverfasser: DAVIS, PAUL G, NGUYEN, DAVID, MACWILLIAMS, PETER D, ABHYANKAR, ABHIJIT M, BARTH, RICHARD M, HOLMAN, THOMAS J, GASBARRO, JAMES A, ANDERSON, ANDREW V, WARE, FREDERICK A, HAMPEL, CRAIG E, STARK, DONALD C
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.