Global signal distribution with reduced routing tracks in an FPGA

The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources. Sharing branches also has the same effect as sharing spines in that the number of branches is reduced by half, also increasing global signal speed. These advantages are achieved without reducing the programming flexibility of the FPGA.