Wafer level dielectric test structure and related method for accelerated endurance testing

An accelerated endurance test structure and process that provides a wafer-level dielectric test. A wafer-level dielectric testing structure includes a heating element. The heating element may be poly-silicon or metal and is formed as a layer above a tunnel oxide layer of an integrated circuit (IC). A thermometer is provided to the heating element to regulate the temperature within the tunnel oxide area. The thermometer may be of a serpentine loop shape. Localized heating of the tunnel oxide structure occurs to a suitable temperature such as 250 DEG Celsius where the endurance test is accelerated so as to assure failure in as little as 10 seconds. Accelerated endurance data on the structure is modeled based on the Arrhenius Equation to accurately predict endurance of the devices contained on the IC.