SRAM memory cell having reduced surface area

A Static RAM cell having a reduced surface area. The Static RAM cell includes a pair of P channel transistors and a pair of N channel transistors connected as a bistable latch. A first common source connection of the latch is connected to a Write Bit terminal and the remaining source connections of the latch are connected to complementary bit lines. A word line addressing the latch is provided through the transistors connected to the Bit Lines having shared body contact which permits reading and writing to the latch. During a write mode, the word line is connected to a potential which renders transistors connected to the complementary bit lines conductive, while the write bit connected to a potential which renders the remaining transistors nonconducting. During a read operation, one of the remaining transistors are rendered conductive, and the word line renders the set of transistors connected to the Bit Lines conductive so that the bit Lines are charged from the respective nodes of the latch.