Method for making a planarized capacitor-over-bit-line structure for dynamic random access memory (DRAM) devices

A method for making a planarized capacitor-over-bit lines structure on dynamic random access memory devices was achieved. After forming the array of FETs for the memory cells, a first polysilicon layer is deposited and patterned to simultaneously form bit lines and polysilicon landing pads that also form the node contacts for stacked capacitors. A thick first insulating layer is deposited and planarized. Node contact openings are etched in the first insulating layer to the landing pads and a thin second polysilicon layer is deposited which also fills the contact openings. Trenches are etched through the second polysilicon layer and into the first insulating layer around the desired capacitor areas while protecting the remaining DRAM chip area from etching. A thin third polysilicon layer is deposited and etched back to form sidewall spacers and to form capacitor bottom electrodes with increased capacitance. A thin interelectrode dielectric layer is deposited followed by a relatively thin fourth polysilicon layer. A photoresist mask is used to pattern the thin fourth polysilicon to form the capacitor plate electrode and to concurrently etch the thin second polysilicon to the planar first insulating layer providing an array of memory cells that are essentially planar with the peripheral areas of the DRAM chip areas.